1. Field of the Invention
The present invention relates to a column analog-to-digital conversion apparatus of a complementary metal-oxide semiconductor (CMOS) image sensor (CIS), and more particularly to a column analog-to-digital conversion apparatus and a method capable of supporting a high frame rate in a sub-sampling mode.
2. Description of Related Art
Compared with charge-coupled devices (CCDs), complementary metal-oxide semiconductor (CMOS) image sensors (CISs) operate at low voltages and have low power consumption. Also, the CMOS image sensors may be implemented in applications needing high-density integration using standard CMOS processes. For these reasons, the CMOS image sensors are widely used in various fields. The CMOS image sensors are expected to replace the CCDs in many fields in the future.
Unlike the CCDs, the CMOS image sensors convert analog signals from an active pixel sensor (APS) array into digital signals. For this conversion, the CMOS image sensors use an analog-to-digital converter (ADC).
The CMOS image sensors may be classified into a single ADC scheme or a column ADC scheme according to an implementation of the analog-to-digital conversion. The single ADC scheme converts APS analog output signals of all columns into digital signals within a given time by using a single ADC that operates at high speed. Although the single ADC scheme can reduce chip area, it has high power consumption as compared to the column ADC scheme because it operates at high speed. The column ADC scheme includes simple ADC circuits provided in each of the columns. The column ADC scheme has a large chip area and low power consumption as compared to the single ADC scheme. The column ADC scheme uses a comparator configured to perform a correlated double sampling (CDS) on APS analog output voltages and store resultant voltages. A ramp voltage generated from a ramp generator is supplied to a comparator. The comparator compares the ramp voltage with the voltage stored during the CDS operation.
As high-resolution images have become increasingly in demand, high-resolution CMOS image sensors have been developed. The high-resolution CMOS image sensors use a sub-sampling mode for supporting a high frame rate when capturing moving images. The high frame rate is supported by reducing the resolution using the sub-sampling mode.
In the case of the CMOS image sensor with the single ADC structure, the number of pixels to be analog-to-digital converted in the sub-sampling mode is reduced by a sub-sampling ratio in row and column directions. Therefore, if the CMOS image sensor operates at the same speed in a full resolution mode, the frame rate increases in proportion to the sub-sampling ratio in the row and column directions in the sub-sampling mode. However, in the sub-sampling mode, the column ADC structure cannot reduce time in the X-direction (refer to FIG. 3) because of its structural characteristics. The time needed to perform the analog-to-digital conversion of one horizontal line cannot be reduced. Consequently, the frame rate is increased by the sub-sampling ratio of the Y-direction.
FIG. 1 is a block diagram illustrating a column-parallel type CMOS image sensor with a CDS structure.
Referring to FIG. 1, the column-parallel type CMOS image sensor includes a row driver 10, an APS array 20, a CDS and comparison circuit 30, and a digital code generator 40.
The CDS and comparison circuit 30 is configured with capacitors and amplifiers for performing independent CDS operations on the respective APS columns and comparing CDS results.
In the sub-sampling mode, one signal of adjacent same-colored pixels is selected and outputted as a pixel output signal APS_OUT according to the sub-sampling ratio. The pixel output signal APS_OUT is converted into a digital code using a ramp signal Vramp and a counting value C0. All values from a most significant bit (MSB) to a least significant bit (LSB) are determined for each pixel output signal in accordance with the counting value C0 outputted from a counter (not shown). For example, if one pixel output signal has a 10-bit resolution, 1,024 clock cycles are needed to convert a signal of a brightest saturation state into a digital signal.
The CMOS image sensor with the column ADC structure cannot reduce a horizontal line time because it uses independent ADC circuits in each of the columns.
Therefore, a need exists for a CMOS image sensor having a reduced horizontal line time.